Periodic testing calls for an electronic system, most often embodied in one or more integrated circuits (ICs) to be intermittently tested during its service life. The system periodically invokes self-test modules (sometimes called infrastructure IPs) that are integrated with the system and designed to test functional circuits in the system when invoked. The result of the self-test is then sampled to determine if any circuit in the system has failed.
The objective of periodic testing is to uncover defects that could occur due to wear and tear resulting from normal use (its “functional mode”) over time. In contrast to critical path monitoring, in which critical path monitors (CPMs) continuously monitor specific paths in a system while it is functioning, periodic testing employs the self-test modules to generate specific tests to detect the presence of new defects.
LBIST takes the form of a self-test module that is integrated into the ICs of a particular system and used for periodic testing. The objective of LBIST-based periodic testing is to uncover defects that could occur due to the wear and tear of the system. Open defects fall in this category (see, e.g., Wadsack, “Fault Modeling and Logic Simulation of CMOS and NMOS Integrated Circuits,” Bell Syst. Tech. Journal, Vol. 57, May-June 1978, pp. 1449-1474). Open defects are unintended high-impedance faults (e.g., stuck-open and stuck-at faults) occurring in the devices, including transistors, or the conductors (e.g., traces and vias) that interconnect them.
FIGS. 1A and 1B are simplified schematic diagrams of transistors containing open defects. FIG. 1A contains an open defect F 110 exhibiting, e.g., a 100 MΩ impedance involving a gate c thereof. FIG. 1B contains an open defect F 120 exhibiting, e.g., a 100 MΩ impedance involving a source or drain b thereof. Gate open defects often result due to the breakdown of interconnects (e.g., vias) driving the gate of the transistor. Open source or drain defects often result from electro-migration stemming from source-drain currents flowing through the transistor.
FIG. 2 shows a popular LBIST architecture, the so-called “STUMPS” (Self-Testing Using an MISR and Parallel Shift Register Sequence Generator) architecture (see, e.g., Bardell, et al., “Self-Testing of Multichip Logic Modules,” IEEE International Test Conference, 1982, pp. 200-204). Circuits-under-test (CUTs) 210, 220 (representing any number of CUTs) are functional circuits in the electronic system that are to be the subject of periodic testing. Many of the transistors in a typical IC are likely to be found in scan chains. Therefore, scan chains are likely locations of open defects. LBIST may be used to apply flush tests to scan chains to test them for open defects.
According to one testing technique, a pseudo-random pattern generator (PRPG) 230 generates and shifts pseudo-random patterns (“scanin_1” through “scanin_n”) into scan chains 250, 260 (“scanchain_1” through “scanchain_n”) corresponding to the CUTs 210, 220 using a scan clock signal (not shown) until the scan-chains 240, 250 are filled. Multiple functional clock signals are then applied at-speed to detect faults in the CUTs 210, 220. Results of the tests (“scanout_1” through “scanout_n”) are then shifted from the scan-chains 240, 250 into a multiple-input scan register (MISR) 260 to yield a signature that can be analyzed. This testing technique is called test-per-scan LBIST.
In a different testing technique, called in-situ, or sometimes test-per-clock, LBIST, the PRPG 230 drives all the inputs of the CUTs 210, 220 and changes state once per clock cycle. A number of different variants of in-situ LBIST are possible. Among them are built-in logic block observation, or BILBO (see, e.g., Konemann, et al., “Built-in Logic Block Observation Techniques,” IEEE International Test Conference, 1979, pp. 37-41) and circular self-test path, or CSTP (see, e.g., Pilarski, et al., “Estimating Testing Effectiveness of Circular Self-Test Path Technique,” IEEE Transactions on Computer-Aided Design, Vol. 11, No. 10, pp. 1301-1316).
Irrespective of the testing technique employed, flip-flops are modified in the CUTs 210, 220 to allow the pseudo-random patterns to be introduced into, and the results to be extracted from, the functional CUTs 210, 220. FIG. 3A shows one example of a scan flip-flop. State elements, such as D flip-flops, may be modified as shown in FIGS. 3B and 3C. In FIGS. 3A-C, yi represent inputs to the CUT, and Yi represent outputs of the CUT. For BILBO, the values of control variables B0, B1 determine the mode of the state elements, viz., functional, scan shift, pattern generation or response compressions. For CSTP, the values of the control variables B0, B1 determine the mode of the state elements, viz., functional, scan shift or response compression. In both cases, the scan shift operation is applied primarily to initialize the contents of the PRPG 230 of FIG. 2 and shift out a compressed signature.